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Freescale Semiconductor Advance Information
MC9328MX1/D Rev. 3.0, 12/2003 MC9328MX1 (i.MX1) Integrated Portable System Processor
MC9328MX1/D Rev. 4, 08/2004
MC9328MX1
MC9328MX1
Package Information Plastic Package (MAPBGA-256)
Ordering Information See Table 2 on page 5
1 Introduction
Motorola's i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the i.MX series provides a leap in performance with an ARM9TM microprocessor core and highly integrated system functions. The i.MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The new MC9328MX1 features the advanced and powerefficient ARM920TTM core that operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller, static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. In addition, the MC9328MX1 is the first BluetoothTM technology-ready applications processor. It is packaged in a 256-pin Mold Array Process-Ball Grid Array (MAPBGA). Figure 1 on page 2 shows the functional block diagram of the MC9328MX1.
Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Signals and Connections . . . . . . . . . . . . . . . . . . . . 6 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Pin-Out and Package Information . . . . . . . . . . . . 93 Contact Information . . . . . . . . . . . . . . . . . . . Last Page
(c) Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice.
Introduction
System Control JTAG/ICE Bootstrap
Power Control
CGM (DPLLx2)
Standard System I/O GPIO
Connectivity MMC/SD Memory Stick(R) Host Controller SPI 1 and SPI 2 UART 1 UART 2 & 3 SSI/I2S 1 & 2 I2C USB Device SmartCard I/F Bluetooth Accelerator AIPI 1
MC9328MX1
CPU Complex ARM9TDMITM
PWM Timer 1 & 2 RTC Watchdog
I Cache
D Cache
Multimedia Multimedia Accelerator Video Port Human Interface Analog Signal Processor LCD Controller
VMMU
Interrupt Controller Bus Control
AIPI 2
DMAC (11 Chnl)
EIM & SDRAMC
eSRAM (128K)
Figure 1. MC9328MX1 Functional Block Diagram
1.1 Conventions
This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. * * LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
MC9328MX1 Advance Information, Rev. 4 2 Freescale Semiconductor
Introduction
1.2 Features
To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including the following: * * * * * * * * * * * * * * * * * * * * * * * * * * ARM920T Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3) Two Serial Peripheral Interfaces (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Multimedia Card and Secure Digital (MMC/SD) Host Controller Module Memory Stick(R) Host Controller (MSHC) SmartCard Interface Module (SIM) Direct Memory Access Controller (DMAC) Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I2S) Module Inter-IC (I2C) Bus Module Video Port General-Purpose I/O (GPIO) Ports Bootstrap Mode Analog Signal Processing (ASP) Module Bluetooth Accelerator (BTA) Multimedia Accelerator (MMA) 256-pin MAPBGA Package
1.3 Target Applications
The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging applications such as Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS interactive communicator.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 3
Introduction
1.4 Document Revision History
The following table provides revision history for this release. This history includes technical content revisions only and not stylistic or grammatical changes.
Table 1. MC9328MX1 Data Sheet Revision History
Revision Location Throughout Table 4 on page 14 Section 3.3, "Power Sequence Requirements" on page 15 Section 3.12, "Bluetooth Accelerator" on page 58 Revision Clarified instances where BCLK signal is burst clock. Maximum Ratings table replaced. Added reference to AN2537. Added "Important" note regarding no software support for the BTA.
1.5 Product Documentation
The following documents are required for a complete description of the MC9328MX1 and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this manual. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MX1 Product Brief (order number MC9328MX1P/D) MC9328MX1S Reference Manual (order number MC9328MX1SRM/D) MC68VZ328 Product Brief (order number MC68VZ328P/D) MC68VZ328 User's Manual (order number MC68VZ328UM/D) MC68VZ328 User's Manual Addendum (order number MC68VZ328UMAD/D) MC68SZ328 Product Brief (order number MC68SZ328P/D) MC68SZ328 User's Manual (order number MC68SZ328UM/D) The Motorola manuals are available on the Motorola Semiconductors Web site at http://www.motorola.com/ semiconductors. These documents may be downloaded directly from the Motorola Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
MC9328MX1 Advance Information, Rev. 4 4 Freescale Semiconductor
Introduction
1.6 Ordering Information
Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA) package.
Table 2. MC9328MX1 Ordering Information
Package Type 256-lead MAPBGA 256-lead MAPBGA 256-lead MAPBGA 256-lead MAPBGA 256-lead MAPBGA 256-lead MAPBGA Frequency 200 MHz 200 MHz 200 MHz 200 MHz 150 MHz 150 MHz Temperature 0C to 70C 0C to 70C -30C to 70C -30C to 70C -40C to 85C -40C to 85C Solderball Type Standard Pb-free Standard Pb-free Standard Pb-free Order Number MC9328MX1VH20(R2) MC9328MX1VM20(R2) MC9328MX1DVH20(R2) MC9328MX1DVM20(R2) MC9328MX1CVH15(R2) MC9328MX1CVM15(R2)
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Signals and Connections
2 Signals and Connections
Table 3 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to.
Table 3. Signal Names and Descriptions
Signal Name Function/Notes External Bus/Chip Select (EIM) A [24:0] D [31:0] EB0 EB1 EB2 EB3 OE CS [5:0] Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24] Byte Strobe--Active low external enable byte signal that controls D [23:16] Byte Strobe--Active low external enable byte signal that controls D [15:8] LSB Byte Strobe--Active low external enable byte signal that controls D [7:0] Memory Output Enable--Active low output enables external data bus Chip Select--The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode of the MC9328MX1 upon system reset is determined by the settings of these pins. SDRAM Controller SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles. SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash cycles. SDRAM address signals SDRAM address signals which are multiplex with address signals A [10:1]. MA [9:0] are selected on SDRAM/SyncFlash cycles.
ECB
LBA
BCLK (burst clock) RW
SDIBA [3:0]
MA [11:10] MA [9:0]
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Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name DQM [3:0] CSD0 SDRAM data enable SDRAM/SyncFlash Chip Select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. SDRAM/SyncFlash Chip Select signal which is multiplex with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as SyncFlash boot chip select by properly configuring BOOT [3:0] input pins. SDRAM/SyncFlash Row Address Select signal SDRAM/SyncFlash Column Address Select signal SDRAM/SyncFlash Write Enable signal SDRAM/SyncFlash Clock Enable 0 SDRAM/SyncFlash Clock Enable 1 SDRAM/SyncFlash Clock SyncFlash Reset Clocks and Resets EXTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when internal oscillator circuit is shut down. Crystal output 32 kHz crystal input 32 kHz crystal output Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock selection. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG TRST TDO TDI Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Function/Notes
CSD1
RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF
XTAL16M EXTAL32K XTAL32K CLKO
RESET_IN
RESET_OUT
POR
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Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name TCK TMS Function/Notes Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. System BIG_ENDIAN BIG_ENDIAN--This signal determines the memory endian configuration. BIG_ENDIAN is a static pin to inner module. If the pin is driven logic-high the memory system is configured into big endian. If it is driven logic-low the memory system is configured into little endian. The pin is not supposed to be changed on the fly. ETM ETMTRACESYNC ETMTRACECLK ETMPIPESTAT [2:0] ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplex with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] CSI_MCLK CSI_VSYNC CSI_HSYNC CSI_PIXCLK Sensor port data Sensor port master clock Sensor port vertical sync Sensor port horizontal sync Sensor port data latch clock LCD Controller LD [15:0] FLM/VSYNC LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. Frame Sync or Vsync--This signal also serves as the clock signal output for gate. driver (dedicated signal SPS for Sharp panel HR-TFT). Line Pulse or H Sync Shift Clock Alternate Crystal Direction/Output Enable This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal).
ETMTRACEPKT [7:0]
LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR
MC9328MX1 Advance Information, Rev. 4 8 Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name PS CLS REV Function/Notes Control signal output for source driver (Sharp panel dedicated signal). Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SIM SIM_CLK SIM_RST SIM_RX SIM_TX SIM_PD SIM_SVEN SIM Clock SIM Reset Receive Data Transmit Data Presence Detect Schmitt trigger input SIM Vdd Enable SPI SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY SPI2_TXD Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready SPI2 Master TxData Output--This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, "Serial Peripheral Interface Modules (SPI 1 and SPI 2)," and Chapter 29, "GPIO Module and I/O Multiplexer (IOMUX)," for information on how to bring this signal to the assigned pin. SPI2 master RxData input--This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, "Serial Peripheral Interface Modules (SPI 1 and SPI 2)," and Chapter 29, "GPIO Module and I/O Multiplexer (IOMUX)," for information on how to bring this signal to the assigned pin. SPI2 Slave Select--This signal is multiplexed with a GPI/O pin, however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, "Serial Peripheral Interface Modules (SPI 1 and SPI 2)," and Chapter 29, "GPIO Module and I/O Multiplexer (IOMUX)," for information on how to bring this signal to the assigned pin. SPI2 Serial Clock--This signal is multiplexed with a GPI/O pin however it does show up as a primary or alternative signal in the signal multiplex scheme table. Refer to Chapter 16, "Serial Peripheral Interface Modules (SPI 1 and SPI 2)," and Chapter 29, "GPIO Module and I/O Multiplexer (IOMUX)," for information on how to bring this signal to the assigned pin.
SPI2_RXD
SPI2_SS
SPI2_SCLK
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 9
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name Function/Notes General Purpose Timers TIN Timer Input Capture or Timer Input Clock--The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USBD_VMO USBD_VPO USBD_VM USBD_VP USBD_SUSPND USBD_RCV USBD_OE USBD_AFE USB Minus Output USB Plus Output USB Minus Input USB Plus Input USB Suspend Output USB RxD USB OE USB Analog Front End Enable Secure Digital Interface SD_CMD SD Command--If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 4.7K-69K external pull up resistor must be added. MMC Output Clock Data--If the system designer does not want to make use of the internal pull-up, via the Pull-up enable register, a 50 K-69K external pull up resistor must be added. Memory Stick Interface MS_BS MS_SDIO MS_SCLKO MS_SCLKI Memory Stick Bus State (Output)--Serial bus control signal Memory Stick Serial Data (Input/Output) Memory Stick Serial Clock (Output)--Serial Protocol clock output Memory Stick External Clock (Input)--Test clock input pin for SCLK divider. This pin is only for test purposes, not for use in application mode. General purpose Input0--Can be used for Memory Stick Insertion/Extraction detect General purpose Input1--Can be used for Memory Stick Insertion/Extraction detect UARTs - IrDA/Auto-Bauding UART1_RXD Receive Data
TMR2OUT
SD_CLK SD_DAT [3:0]
MS_PI0 MS_PI1
MC9328MX1 Advance Information, Rev. 4 10 Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR UART2_RI UART2_DCD UART2_DTR UART3_RXD UART3_TXD UART3_RTS UART3_CTS UART3_DSR UART3_RI UART3_DCD UART3_DTR Transmit Data Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Ports - SSI (configurable to I2S protocol) SSI1_TXDAT SSI1_RXDAT SSI1_TXCLK SSI1_RXCLK SSI1_TXFS SSI1_RXFS SSI2_TXDAT SSI2_RXDAT TxD RxD Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync TxD RxD Function/Notes
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 11
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name SSI2_TXCLK SSI2_RXCLK SSI2_TXFS SSI2_RXFS Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C_SDA I2C Clock I2C Data PWM PWMO PWM Output ASP UIN UIP PX1 PY1 PX2 PY2 R1A R1B R2A R2B RVP RVM AVDD AGND Positive U analog input (for low voltage, temperature measurement) Negative U analog input (for low voltage, temperature measurement) Positive pen-X analog input Positive pen-Y analog input Negative pen-X analog input Negative pen-Y analog input Positive resistance input (a) Positive resistance input (b) Negative resistance input (a) Negative resistance input (b) Positive reference for pen ADC Negative reference for pen ADC Analog power supply Analog ground BlueTooth BT1 BT2 I/O clock signal Output Function/Notes
MC9328MX1 Advance Information, Rev. 4 12 Freescale Semiconductor
Signals and Connections
Table 3. Signal Names and Descriptions (Continued)
Signal Name BT3 BT4 BT5 BT6 BT7 BT8 BT9 BT10 BT11 BT12 BT13 TRISTATE BTRF VDD BTRF GND Input Input Output Output Output Output Output Output Output Output Output Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal operations. Power supply from external BT RFIC Ground from external BT RFIC Noisy Supply Pins NVDD NVSS Noisy Supply for the I/O pins Noisy Ground for the I/O pins Supply Pins - Analog Modules AVDD AVSS Supply for analog blocks Quiet GND for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry GND pins for silicon internal circuitry Function/Notes
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Specifications
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 15 or the DC Characteristics table.
Table 4. Maximum Ratings1
Symbol NVdd QVdd AVdd BTRFVdd Vdd TA TA TA VESD_HBM VESD_MM ILatchup Test Pmax 1. 2. 3. DC I/O Supply Voltage DC Internal (core) Supply Voltage DC Analog Supply Voltage DC Bluetooth Supply Voltage Supply voltage Maximum operating temperature range MC9328MX1VH20/MC9328MX1VM20 Maximum operating temperature range MC9328MX1DVH20/MC9328MX1DVM20 Maximum operating temperature range MC9328MX1CVH15/MC9328MX1CVM15 ESD at human body model (HBM) ESD at machine model (MM) Latch-up current Storage temperature Power Consumption Rating Minimum - - - - -0.3 0 Maximum - - - - 3.3 70 Unit V V V V V C
-30
70
C
-40
85
C
- - - -55 8002
2000 100 200 150 13003
V V mA C mW
Voltages referenced to Vss and BTRFGND, which are both tied to the same potential. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS application at 200MHz, and where the whole image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
MC9328MX1 Advance Information, Rev. 4 14 Freescale Semiconductor
Specifications
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages. The MC9328MX1 processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as other NVDD pins. For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.
Table 5. Recommended Operating Range 1
Symbol NVDD Rating I/O supply voltage MSHC, SPI, BTA, USBd, LCD and CSI are only 3V interface Minimum 2.70 Maximum 3.30 Unit V
NVDD QVDD
I/O supply voltage Internal supply voltage (Core = 150 MHz) Internal supply voltage (Core = 200 MHz) Analog supply voltage Bluetooth I/O voltage (Bluetooth)
1.70 1.70
3.30 1.90
V V
QVDD
1.80
2.00
V
AVDD BTRFVD D1 BTRFVD D2 1.
1.70 1.70
3.30 3.10
V V
Bluetooth I/O voltage (Non Bluetooth applications)
1.70
3.30
V
Voltages referenced to Vss and BTRFGND, which are both tied to the same potential.
3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the "Power-Up Sequence" section of application note AN2537 on the i.MX website page.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1.
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Specifications
Table 6. Maximum and Minimum DC Characteristics
Number or Symbol Iop Parameter Full running operating current at 1.8V for QVDD, 3.3V for NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4 decoding playback from external memory card to both external SSI audio decoder and TFT display panel, and OS with MMU enabled memory system is running on external SDRAM) Please refer to application note: AN2537, Power Performance of MC9328MX1. Standby current (QVDD = 1.8V, temp = 25C) Standby current (QVDD = 1.8V, temp = 55C) Standby current (QVDD = 2.0V, temp = 25C) Standby current (QVDD = 2.0V, temp = 55C) Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Input low leakage current (VIN = GND, no pull-up or pull-down) Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is tri-stated) Input capacitance Output capacitance Minimum - Typical QVDD at 1.8v = 120mA; NVDD+AVDD at 3.0v = 30mA Maximum - Unit mA
Sidd1 Sidd2 Sidd3 Sidd4 VIH VIL VOH VOL IIL IIH IOH IOL IOZ Ci Co
- - - - 0.7VDD - 0.7VDD - -
25 45 35 60 - - - - -
- - - - Vdd+0.2 0.4 Vdd 0.4 1
A A A A V V V V A A
-
-
1
-
-
4.0
mA
-4.0
-
-
-
mA A
-
5
- -
- -
5 5
pF pF
MC9328MX1 Advance Information, Rev. 4 16 Freescale Semiconductor
Specifications
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading.
Table 7. Tri-State Signal Timing
Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum - Maximum 20.8 Unit ns
Table 8. 32k/16M Oscillator Signal Timing
Parameter EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL EXTAL32k input jitter (peak to peak) for MCUPLL only EXTAL32k startup time EXTAL16M input jitter (peak to peak) EXTAL16M startup time Minimum - RMS 5 Maximum 20 Unit ns
- 800 - TBD
5 - TBD -
100 - TBD -
ns ms - -
Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
Best Case Rise Time Fall Time 0.80 0.74 Typical 1.00 1.08 Worst Case 1.40 1.67 Units ns ns
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Specifications
3.6 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: * * * 32-bit data field 7-bit address field A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 10 on page 18 for the ETM9 timing parameters used in Figure 2.
2a 3a
TRACECLK
1 2b
3b
TRACECLK (Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
4b
Figure 2. Trace Port Timing Diagram Table 10. Trace Port Timing Diagram Parameter Table
1.8V +/- 0.10V Ref No. Parameter Minimum 1 2a 2b 3a 3b 4a 4b CLK frequency Clock high time Clock low time Clock rise time Clock fall time Output hold time Output setup time 0 1.3 3 - - 2.28 3.42 Maximum 85 - - 4 3 - - Minimum 0 2 2 - - 2 3 Maximum 100 - - 3 3 - - MHz ns ns ns ns ns ns 3.0V +/- 0.30V Unit
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Specifications
3.7 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, Tref is a reference clock period after the pre-divider and Tdck is the output double clock period.
Table 11. DPLL Specifications
Parameter Reference clock freq range Pre-divider output clock freq range Double clock freq range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset Freq lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) Vcc = 1.8V Vcc = 1.8V Test Conditions Minimum 5 5 Typical - - Maximum 100 30 Unit MHz MHz
Vcc = 1.8V - Includes both integer and fractional parts -
80 1 5
- - -
220 16 15
MHz - -
5
-
15
-
Should be less than the denominator -
0
-
1022
-
1
-
1023
-
- FOL mode for non-integer MF (does not include pre-must lock-in time) FOL mode for non-integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) FPL mode and integer MF (does not include pre-multi lock-in time) -
- 250
- 280 (56 s) 250 (~50 s) 350 (70 s) 320 (64 s) 0.005 (0.01%) 1.0 (10%) - -
312.5 300
sec
Tref Tref Tref Tref 2*Tdck ns
220
270
300
400
270
370
-
0.01
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
-
1.5
Power supply voltage Power dissipation
- FOL mode, integer MF, fdck = 200 MHz, Vcc = 1.8V
1.7 -
2.5 4
V mW
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 19
Specifications
3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4.
NOTE:
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing.
90% AVDD 1 POR 10% AVDD
RESET_POR
2 Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM 4 HRESET RESET_OUT
14 cycles @ CLK32
CLK32
HCLK
Figure 3. Timing Relationship with POR
MC9328MX1 Advance Information, Rev. 4 20 Freescale Semiconductor
Specifications
5 RESET_IN
14 cycles @ CLK32
HRESET
RESET_OUT 6 4
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN Table 12. Reset Module Timing Parameter Table
Ref No. 1 2 1.8V +/- 0.10V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (9600 *CLK32 at 32 KHz) 7K to 32K-cycle stretcher for SDRAM reset note1 300 Max - 300 Min note1 300 Max - 300 - ms 3.0V +/- 0.30V Unit
3
7
7
7
7
Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32
4
14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN
14
14
14
14
5
4
-
4
-
6
4K to 32K-cycle qualifier
4
4
4
4
1.
POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in calculating timing for the start-up process.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 21
Specifications
3.9 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 13 defines the parameters of signals.
(HCLK) Bus Clock
1a 1b
Address Chip-select
2a 2b
3a
3b
Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge)
6a 5a 4a 4b
4c
4d
5b
5c
5d
LBA (negated falling edge)
6b
LBA (negated rising edge)
6a
6c
7a
7b
BCLK (burst clock) - rising edge BCLK (burst clock) - falling edge
7c
7d
8b
Read Data
9a 8a 9b
Write Data (negated falling)
9a 9c
Write Data (negated rising) DTACK_B
10a 10a
Figure 5. EIM Bus Timing Diagram Table 13. EIM Bus Timing Parameter Table
1.8 0.10V Ref No. Parameter Min 1a Clock fall to address valid 2.48 Typical 3.31 Max 9.11 Min 2.4 Typical 3.2 Max 8.8 ns 3.0 0.3V Unit
MC9328MX1 Advance Information, Rev. 4 22 Freescale Semiconductor
Specifications
Table 13. EIM Bus Timing Parameter Table (Continued)
1.8 0.10V Ref No. Parameter Min 1b 2a 2b 3a 3b 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 1. Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid Clock1 rise to Output Enable Valid Clock1 rise to Output Enable Invalid Clock1 fall to Output Enable Valid Clock1 fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock1 rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid Clock1 rise to Load Burst Address Invalid Clock1 rise to Burst Clock rise Clock1rise to Burst Clock fall Clock1 fall to Burst Clock rise Clock1 fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock1 fall to Write Data Invalid Clock1 rise to Write Data Invalid DTACK setup time 1.55 2.69 1.55 1.35 1.86 2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52 Typical 2.48 3.31 2.48 2.79 2.59 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 - - 2.72 2.48 - - Max 5.69 7.87 6.31 6.52 6.11 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 - - 6.85 5.69 - - Min 1.5 2.6 1.5 1.3 1.8 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 2.4 3.2 2.4 2.7 2.5 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 - - 2.7 2.4 - - Max 5.5 7.6 6.1 6.3 5.9 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 - - 6.8 5.5 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0 0.3V Unit
Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 23
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
(3)
Address
(2)
CS5
(8) (1)
EB
programmable min 0ns
(5)
(9)
OE
(4)
DTACK
(6)
Databus (input to MX1) (10)
(7)
Figure 6. DTACK READ Cycle without DMA Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 0.3) V Number Characteristic Minimum 1 2 3 4 OE and EB assertion time CS5 pulse width OE negated to address inactive DTACK asserted after CS5 asserted See note 2 3T 46.44 - Maximum - - - 1019T ns ns ns ns Unit
MC9328MX1 Advance Information, Rev. 4 24 Freescale Semiconductor
Specifications
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
(3.0 0.3) V Number Characteristic Minimum 5 6 7 8 9 10 DTACK asserted to OE negated Data hold timing after OE negated Data ready after DTACK asserted OE negated to CS negated OE negated after EB negated DTACK pulse width 3T+2.2 0 0 0.5T+0.24 0.5 1T Maximum 4T+6.86 - T 0.5T+0.67 1.5 3T ns ns ns ns ns ns Unit
Note: 0. DTACK assert means DTACK become low level. 1. T is the system clock period. (For 96MHz system clock) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.2 DTACK Read Cycle DMA Enabled
(4)
Address
(2)
CS5
(9)
(1)
EB
programmable min 0ns
(6)
(10) (3)
OE
RW (logic high) DTACK
(5) (7)
(11)
Databus (input to MX1)
(8)
Figure 7. DTACK Read Cycle DMA Enabled
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 25
Specifications
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 0.3) V Number Characteristic Minimum 1 2 3 4 5 6 7 8 9 10 11 OE and EB assertion time CS pulse width OE negated before CS5 is negated Address inactive before CS negated DTACK asserted after CS5 asserted DTACK asserted to OE negated Data hold timing after OE negated Data ready after DTACK is asserted CS deactive to next CS active OE negate after EB negate DTACK pulse width See note 2 3T 0.5T+0.24 - - 3T+2.2 0 - T 0.5 1T Maximum - - 0.5T+0.67 0.93 1019T 4T+6.86 - T - 1.5 3T ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 0. DTACK assert mean DTACK become low. 1. T is the system clock period. (For 96MHz system clock) 2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MX1 Advance Information, Rev. 4 26 Freescale Semiconductor
Specifications
3.9.2.3 DTACK Write Cycle without DMA
(5)
Address
(1)
CS5
(3)
programmable min 0ns
(10)
(2)
EB
programmable min 0ns
(7)
(4)
RW
OE (logic high) DTACK
(6) (9)
(11)
Databus (output from MX1)
(8)
Figure 8. DTACK Write Cycle without DMA Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(3.0 0.3) V Number Characteristic Minimum 1 2 3 4 5 6 7 8 9 10 11 CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated RW negated to Address inactive DTACK asserted after CS5 asserted DTACK asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted EB negated before CS5 is negated DTACK pulse width See note 2. See note 2 3T 1.5T+0.58 57.31 - 2T+1.8 1.5T-0.59 - 0.5T+0.74 1T Maximum - - - 1.5T+1.58 - 1019T 3T+5.26 - T 0.5T+2.17 3T ns ns ns ns ns ns ns ns ns ns ns Unit
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 27
Specifications
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
(3.0 0.3) V Number Characteristic Minimum Note:
0. DTACK assert mean DTACK become low. 1. T is the system clock period. (For 96MHz system clock) 2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Unit Maximum
3.9.2.4 DTACK Write Cycle DMA Enabled
(5)
Address
(1)
CS5
(3)
programmable min 0ns
(11)
(10)
(2)
EB
programmable min 0ns
(7) (4)
RW
OE (logic high) DTACK
(6) (9)
(12)
Databus (output from MX1)
(8)
Figure 9. DTACK Write Cycle DMA Enabled Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
(3.0 0.3) V Number Characteristic Minimum 1 2 3 4 5 6 CS5 assertion time EB assertion time CS5 pulse width RW negated before CS5 is negated Address inactive before CS negated DTACK asserted after CS5 asserted See note 2 See note 2 3T 1.5T+0.58 - - Maximum - - - 1.5T+1.58 0.93 1019T ns ns ns ns ns ns Unit
MC9328MX1 Advance Information, Rev. 4 28 Freescale Semiconductor
Specifications
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
(3.0 0.3) V Number Characteristic Minimum 7 8 9 10 11 12 Note:
0. DTACK assert mean DTACK become low. 1. T is the system clock period. (For 96MHz system clock) 2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register. 3. Address becomes valid and RW asserts at the start of write access cycle. 4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Unit Maximum 3T+5.26 - T - 0.5T+2.17 3T ns ns ns ns ns ns 2T+1.8 1.5T-0.59 - T 0.5T+0.74 1T
DTACK asserted to RW negated Data hold timing after RW negated Data ready after CS5 is asserted CS deactive to next CS active EB negate to CS negate DTACK pulse width
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 29
Specifications
3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral.
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[0] htrans Seq/Nonseq
hwrite
Read
haddr hready weim_hrdata weim_hready
V1
Last Valid Data
V1
BCLK (burst clock) ADDR CS2 R/W Last Valid Address V1
Read
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 30 Freescale Semiconductor
Specifications
hclk hsel_weim_cs[0] Internal signals - shown only for illustrative purposes htrans hwrite haddr Nonseq
Write
V1
hready
hwdata weim_hrdata
Last Valid Data
Write Data (V1)
Unknown
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS0 R/W LBA Write Last Valid Address V1
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 31
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[0]
htrans hwrite haddr
Nonseq Read V1
hready weim_hrdata Last Valid Data V1 Word
weim_hready
BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Read
EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 32 Freescale Semiconductor
Specifications
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[0] Nonseq
htrans hwrite haddr
Write V1
hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS0 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Write
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 33
Specifications
hclk
Internal signals - shown only for illustrative purposes
hsel_weim_cs[3] htrans hwrite haddr Nonseq
Read V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready BCLK (burst clock) ADDR Last Valid Addr CS[3] R/W Read Address V1 Address V1 + 2
BA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 34 Freescale Semiconductor
Specifications
hclk hsel_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data weim_hrdata Nonseq
Internal signals - shown only for illustrative purposes
Write V1
Write Data (V1 Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr CS3 R/W LBA OE Write Address V1 Address V1 + 2
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 35
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Read
hwrite haddr
V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock) ADDR CS2 R/W Read Last Valid Addr Address V1 Address V1 + 2
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 36 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq
hwrite haddr
Write V1
hready hwdata Last Valid Data weim_hrdata
Write Data (V1 Word)
Last Valid Data
weim_hready BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W LBA OE
Write
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 37
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans
Nonseq Read V1
hwrite haddr
hready weim_hrdata Last Valid Data V1 Word
weim_hready BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V1 + 2
CS2 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 38 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Read
hwrite haddr
V1
hready weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock) ADDR CS2 Read Last Valid Addr Address V1 Address V1 + 2
R/W
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 39
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Write
hwrite haddr
V1
hready Last Valid Data
hwdata weim_hrdata
Write Data (V1 Word)
Unknown
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA OE EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 40 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
htrans
Nonseq Write
hwrite haddr
V1
hready hwdata Last Valid Data weim_hrdata
Write Data (V1 Word) Last Valid Data
Unknown
weim_hready
BCLK (burst clock) ADDR CS2 Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA
OE EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 41
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] Nonseq Read Nonseq Write
htrans
hwrite haddr
V1
V8
hready
hwdata weim_hrdata
Last Valid Data Last Valid Data
Write Data Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8
CS2
R/W LBA
Read
Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data
DATA
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 42 Freescale Semiconductor
Specifications
Read hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2]
Idle
Write
htrans
Nonseq Read
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
Last Valid Data
Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 Address V8
CS2 R/W LBA Read Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 43
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[4]
htrans
Nonseq Write
hwrite haddr
V1
hready hwdata Last Valid Data weim_hrdata
Write Data (Word)
Last Valid Data
weim_hready
BCLK (burst clock) ADDR CS Last Valid Addr Address V1 Address V1 + 2
R/W
Write
LBA OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 44 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4]
htrans
Nonseq Read
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata weim_hrdata weim_hready
Last Valid Data Last Valid Data
Write Data Read Data
BCLK (burst clock) ADDR CS4 Last Valid Addr Address V1 Address V8
R/W LBA
Read
Write
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data
DATA
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 45
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[4] htrans
Nonseq Read
Idle
Seq Read
hwrite haddr
V1
V2
hready weim_hrdata weim_hready
Last Valid Data
Read Data (V1)
Read Data (V2)
BCLK (burst clock) ADDR
Last Valid
Address V1 CNC
Address V2
CS4 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA
Read Data (V1)
Read Data (V2)
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 46 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[4]
htrans
Nonseq Read
Idle
Nonseq Write
hwrite haddr
V1
V8
hready
hwdata weim_hrdata
Last Valid Data Last Valid Data
Write Data Read Data
weim_hready
BCLK (burst clock) ADDR Last Valid Addr Address V1 CNC CS4 R/W LBA OE Address V8
Read
Write
EBx1 (EBC2=0) EBx1 (EBC2=1)
DATA DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 47
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr
Nonseq Read V1
Nonse Read V5
Idle
hready
weim_hrdata weim_hready BCLK (burst clock) ADDR
Last Valid Addr
Address V1
Address V5
CS2 Read
R/W LBA
OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V5 Word
V6 Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MX1 Advance Information, Rev. 4 48 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes hsel_weim_cs[2] htrans hwrite haddr Idle
Nonseq Read V1
Seq Read V2
Seq Read V3
Seq Read V4
hready
weim_hrdata weim_hready BCLK (burst clock)
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
ADDR Last Valid Addr CS2 R/W
Address V1
Read
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 49
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] htrans Idle
Nonseq
Seq
hwrite haddr
Read V1
Read V2
hready weim_hrdata Last Valid Data V1 Word V2 Word
weim_hready BCLK (burst clock) ADDR CS2 Read Last Valid Address V1 Address V2
R/W
LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
ECB DATA V1 1/2 V1 2/2 V2 1/2 V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 50 Freescale Semiconductor
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] Non seq Read
htrans
Seq
Idle
hwrite haddr
Read
V1
V2
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready BCLK (burst clock) Last
ADDR CS2
Address V1
R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
Read
ECB DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 51
Specifications
hclk Internal signals - shown only for illustrative purposes
hsel_weim_cs[2] htrans Non seq Read V1
Seq
Idle
hwrite haddr
Read V2
hready weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready BCLK (burst clock) ADDR CS2 Last Address V1
R/W LBA OE EBx1 (EBC2=0) EBx1 (EBC2=1)
Read
ECB DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3 Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MX1 Advance Information, Rev. 4 52 Freescale Semiconductor
Specifications
LSCLK
LD[15:0]
1
Figure 33. SCLK to LD Timing Diagram Table 18. LCDC SCLK Timing
3.0 +/- 0.3V Num 1 Characteristic SCLK to LD valid Minimum - Maximum 3 Unit ns
3.9.4 Non-TFT Panel Timing
T1 VSYN T1
T2 HSYN SCLK
T3
XMAX
T4
T2
Ts LD[15:0] Figure 34. Non-TFT Panel Timing Table 19.
Symbol T1 T2 T3 T4 Parameter HSYN to VSYN delay HSYN pulse width VSYN to SCLK SCLK to HSYN
Non TFT Panel Timing Diagram
Allowed Register Minimum Value 0 0 - 0 Actual Value HWAIT2+2 HWIDTH+1 0<= T3<=Ts HWAIT1+1 Unit Tpix Tpix - Tpix
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 53
Specifications
* * * * * *
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high. Ts is the shift clock period. Ts = Tpix * (panel data bus width). Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
MC9328MX1 Advance Information, Rev. 4 54 Freescale Semiconductor
Specifications
3.10 Pen ADC Specifications
The specifications for the pen ADC are shown in Table 20 through Table 22.
Table 20. Pen ADC System Performance
Full Range Resolution1 Non-Linearity Error1 Accuracy 1 1. 13 bits 4 bits 9 bits
Tested under input = 0~1.8V at 25C
Table 21. Pen ADC Test Conditions
Vp max Vp min Vn 1800 mV GND GND ip max ip min in 12 MHz 1.2 KHz 100 Hz 0-1800 mV +7 A 1.5 A 1.5 A
Sample frequency Sample rate Input frequency Input range Note:
Ru1 = Ru2 = 200K
Table 22. Pen ADC Absolute Rating
ip max ip min in max in min +9.5 A -2.5 A +9.5 A -2.5 A
3.11 ASP Touch Panel Controller
The following sections contain the electrical specifications of the ASP touch panel controller. The value of parameters and their corresponding measuring conditions are mentioned as well.
3.11.1 Electrical Specifications
Test conditions: Temperature = 25 C, QVDD = 1800mV.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 55
Specifications
Table 23. ASP Touch Panel Controller Electrical Spec
Parameter Offset Offset Error Gain Gain Error DNL INL Accuracy (without missing code) Operating Voltage Range (Pen) Operating Voltage Range (U) On-resistance of switches SW[8:1] Note that QVDD should be 1800mV. Minimum - - - - 8 - 8 - Negative QVDD - Type 32768 - 13.65 - 9 0 9 - - 10 Maximum - 8199 - 33% - - - QVDD QVDD - Unit - - mV-1 - Bits Bits Bits mV mV Ohm
3.11.2 Gain Calculations
The ideal mapping of input voltage to output digital sample is defined as follows:
Sample
65535 Smax
G0
C0
Vi -2400 1800 2400
Figure 35. Gain Calculations
In general, the mapping function is: S=G*V+C Where V is input, S is output, G is the slope, and C is the y-intercept. Nominal Gain G0 = 65535 / 4800 = 13.65mV-1 Nominal Offset C0 = 65535 / 2 = 32767
MC9328MX1 Advance Information, Rev. 4 56 Freescale Semiconductor
Specifications
3.11.3 Offset Calculations
The ideal mapping of input voltage to output digital sample is defined as:
Sample
65535 Smax
G0
C0
Vi -2400 1800 2400
Figure 36. Offset Calculations
In general, the mapping function is: S=G*V+C Where V is input, S is output, G is the slope, and C is the y-intercept. Nominal Gain G0 = 65535 / 4800 = 13.65mV-1 Nominal Offset C0 = 65535 / 2 = 32767
3.11.4 Gain Error Calculations
Gain error calculations are made using the information in this section.
Sample
Gmax 65535 Smax G0
C0
Vi - 2400 1800 2400
Figure 37. Gain Error Calculations
Assuming the offset remains unchanged, the mapping is rotated around y-intercept to determine the maximum gain allowed. This occurs when the sample at 1800mV has just reached the ceiling of the 16-bit range, 65535.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 57
Specifications
Maximum Offset Gmax, Gmax = (65535 - C0) / 1800 = (65535 - 32767) / 1800 = 18.20 = (Gmax - G0) / G0 * 100% = (18.20 - 13.65) / 13.65 * 100% = 33%
Gain Error Gr, Gr
3.12 Bluetooth Accelerator
IMPORTANT:
On-chip accelerator hardware is not supported by software. An external Bluetooth chip interfaced to a UART is recommended.
The Bluetooth Accelerator (BTA) radio interface supports the Motorola Radio, MC13180 using an SPI interface. This section provides the data bus timing diagrams and SPI interface timing diagrams shown in Figure 38 and Figure 39 on page 59, and the associated parameters shown in Table 24 and Table 25 on page 59.
2 BT CLK (BT1)
7 FS (BT5)
Receive
1
PKT DATA (BT3) 3 4
RXTX_EN (BT9) 8 PKT DATA (BT2) 5 6
Transmit
Figure 38. Motorola MC13180 Data Bus Timing Diagram Table 24. Motorola MC13180 Data Bus Timing Parameter Table
Ref No. 1 2 Parameter FrameSync setup time relative to BT CLK rising edge1 FrameSync hold time relative to BT CLK rising edge1 Minimum - - Typical 4 12 Maximum - - Unit ns ns
MC9328MX1 Advance Information, Rev. 4 58 Freescale Semiconductor
Specifications
Table 24. Motorola MC13180 Data Bus Timing Parameter Table (Continued)
Ref No. 3 4 5 6 7 8 1. 2. Parameter Receive Data setup time relative to BT CLK rising edge1 Receive Data hold time relative to BT CLK rising edge1 Transmit Data setup time relative to RXTX_EN rising edge2 TX DATA period BT CLK duty cycle Transmit Data hold time relative to RXTX_EN falling edge 40 4 Minimum - - 172.5 Typical 6 13 - 1000 +/- 0.02 - - 60 10 Maximum - - 192.5 Unit ns ns s ns % s
Please refer to Motorola 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation. The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and RF_Status (0x0021605C) registers.
1
4
5
6
SPI CLK (BT13) 9 SPI_EN (BT11) 8 SPI_DATA_OUT (BT12) 3 SPI_DATA_IN (BT4) 7
2
Figure 39. SPI Interface Timing Diagram Using Motorola MC13180 Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180
Ref No. 1 2 3 4 5 6 Parameter SPI_EN setup time relative to rising edge of SPI_CLK Transmit data delay time relative to rising edge of SPI_CLK Transmit data hold time relative to rising edge of SPI_EN SPI_CLK rise time SPI_CLK fall time SPI_EN hold time relative to falling edge of SPI_CLK Minimum 15 0 0 0 0 15 Maximum - 15 15 25 25 - Unit ns ns ns ns ns ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 59
Specifications
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180 (Continued)
Ref No. 7 8 9 1. Parameter Receive data setup time relative to falling edge of SPI_CLK1 Receive data hold time relative to falling edge of SPI_CLK1 SPI_CLK frequency, 50% duty cycle required1 Minimum 15 15 - Maximum - - 20 Unit ns ns MHz
The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by programming SPI_Control (0x00216138) register together with system clock.
3.13 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external SPI master's timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO.
.
2 SS 1 SPIRDY
3
5
4
SCLK, MOSI, MISO
Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
MC9328MX1 Advance Information, Rev. 4 60 Freescale Semiconductor
Specifications
SS (output)
SCLK, MOSI, MISO
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input) 6 SCLK, MOSI, MISO 7
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 26. Timing Parameter Table for Figure 40 through Figure 44
Ref No. 1 2 3 4 5 6 7 1. 2. 3. Parameter SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width Minimum 2T 1 3*Tsclk 2 2*Tsclk 0 Tsclk + WAIT 3 T T Maximum - - - - - - - Unit ns ns ns ns ns ns ns
T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample Period Control Register.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 61
Specifications
3.14 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MX1 Reference Manual.
LSCLK
LD[15:0]
1
Figure 45. SCLK to LD Timing Diagram Table 27. LCDC SCLK Timing Parameter Table
Ref No. 1 Parameter SCLK to LD valid Minimum - Maximum 2 Unit ns
Non-display region
T1 T3
Display region T4
VSYN HSYN OE LD[15:0]
T2
Line Y
Line 1
Line Y
T5 HSYN SCLK OE LD[15:0] VSYN
T6
XMAX
T7
T8
(1,1) (1,2) (1,X)
Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Diagram
MC9328MX1 Advance Information, Rev. 4 62 Freescale Semiconductor
Specifications
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table
Symbol T1 Description End of OE to beginning of VSYN Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 1 -3 2 Corresponding Register Value (VWAIT1*T2)+T5+T6+T7+T9 Unit Ts
T2 T3 T4 T5 T6 T7 T8 T9
HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 End of OE to beginning of HSYN SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) VSYN to OE active (Sharp = 0), when VWAIT2 = 0 VSYN to OE active (Sharp = 1), when VWAIT2 = 0
XMAX+T5+T6+T7+T9+T10 VWIDTH*(T2) VWAIT2*(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 3 2
Ts Ts Ts Ts Ts Ts ns Ts
T9
1
1
Ts
T10
1
1
Ts
T10
2
2
Ts
Note:
* * * * * * Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 63
Specifications
3.15 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming).
3a 3b
Bus Clock
1
2 4b
4a 5a
CMD_DAT Input
Valid Data
5b
Valid Data
7
CMD_DAT Output
Valid Data Valid Data
6a
6b
Figure 47. Chip-Select Read Cycle Timing Diagram Table 29. SDHC Bus Timing Parameter Table
Ref No. 1 2 3a 3b 4a 4b 5a 5b 6a 6b 7 1. 2. 3. 1.8V +/- 0.10V Parameter Min CLK frequency at Data transfer Mode (PP)1--10/30 cards CLK frequency at Identification Mode2 Clock high time1--10/30 cards Clock low time1--10/30 cards Clock fall time1--10/30 cards Clock rise time1--10/30 cards Input hold time3--10/30 cards Input setup time3--10/30 cards Output hold time3--10/30 cards Output setup time3--10/30 cards Output delay time3 CL 100 pF / 250 pF (10/30 cards) CL 250 pF (21 cards) CL 25 pF (1 card) 0 0 6/33 15/75 - - 5.7/5.7 5.7/5.7 5.7/5.7 5.7/5.7 0 Max 25/5 400 - - 10/50 (5.00)3 14/67 (6.67)3 - - - - 16 Min 0 0 10/50 10/50 - - 5/5 5/5 5/5 5/5 0 Max 25/5 400 - - 10/50 10/50 - - - - 14 MHz KHz ns ns ns ns ns ns ns ns ns 3.0V +/- 0.30V Unit
MC9328MX1 Advance Information, Rev. 4 64 Freescale Semiconductor
Specifications
3.15.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30.
Table 30. State Signal Parameters for Figure 48 through Figure 52
Card Active Symbol Z D Definition High impedance state Data bits Symbol S T Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) Host Active Definition
* CRC
Repetition Cyclic redundancy check bits (7 bits)
P E
NID cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
Identification Timing NCR cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ
SET_RCA Timing
Figure 48. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49 on page 66, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 65
Specifications
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** PST Response Content CRC E Z Z Z
Command response timing (data transfer mode)
NRC cycles Response CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
NCC cycles Host Command CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 50 on page 67 shows basic read operation timing. In a read operation, the sequence starts with a single block read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of the stop command.
MC9328MX1 Advance Information, Rev. 4 66 Freescale Semiconductor
Specifications
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
Z Z P ****** P S D D D D
*****
NAC cycles
Read Data Timing of single block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z
DAT
Z****Z
ZZP
******
P S DDDD
*****
P
*****
P S DDDD
*****
Read Data NAC cycles NAC cycles
Read Data
Timing of multiple block read
NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T NST DAT D D D D ***** DDDDE Z Z Z ***** Timing of stop command (CMD12, data transfer mode) Response Content CRC E Z
Valid Read Data
Figure 50. Timing Diagrams at Data Read
Figure 51 on page 68 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 67
68
NCR cycles Host Command Response ****** Content ****** PST CRC E Z Z P PP P CMD S T Content CRC E Z Z P DAT Z****Z Content Content Write Data Timing of the block write command NWR cycles CRC status Z****Z Z ZZPPS DAT Z ZZPPS CRC E Z Z S Status ES L*L EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CMD E Z Z P ****** Content Status CRC E Z Z S EZPPS Content CRC E Z Z S Status ES L*L DAT Z Z P P S PPP EZ DAT Z Z P P S Content Write Data CRC status CRC E Z Z X X X X X X X X Z P P S Content Write Data CRC status NWR cycles CRC E Z Z X X X X X X X X X X X X X X X X Z Busy NWR cycles Timing of the multiple block write command
Specifications
Figure 51. Timing Diagrams at Data Write
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
Freescale Semiconductor
NCR cycles Host Command Card Response ****** PST Content CRC E Z Z Z ST CMD S T Content CRC E Z Z P Host Command Content CRC E DAT D D D D D D D D D D D D D E Z Z S L ****** Write Data Busy (Card is programming) DAT D D D D D D D Z Z S CRC E Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during data transfer from the host. EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during CRC status transfer from the card. DAT S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming. DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming.
The stop transmission command may occur when the card is in different states. Figure 52 shows the different scenarios on the bus.
Figure 52. Stop Transmission During Different Scenarios
MC9328MX1 Advance Information, Rev. 4
Specifications
69
Specifications
Table 31. Timing Values for Figure 48 through Figure 52
Parameter Symbol Minimum Maximum Unit
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Command read cycle Command-command cycle Command write cycle Stop transmission cycle NCR NID NAC NRC NCC NWR NST 2 5 2 8 8 2 2 64 5 TAAC + NSAC - - - 2 Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles
TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104]
3.15.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (SD_DAT[1] returns to its high level). In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period" during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes).
CMD
ST
Content
CRC E Z Z P S
Response
EZZZ
******
ZZZ
DAT[1] For 4-bit
Interrupt Period
S
Block Data
E
IRQ
S
Block Data
E
IRQ
LH DAT[1] For 1-bit
Interrupt Period
Figure 53. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues.
MC9328MX1 Advance Information, Rev. 4 70 Freescale Semiconductor
Specifications
CMD
******
P S T CMD52
CRC E Z Z Z
******
DAT[1] For 4-bit DAT[2] For 4-bit
S
Block Data
EZZL H
S
Block Data
E
S
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S
Block Data
E
Figure 54. SDIO ReadWait Timing Diagram
3.16 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in either four-state or two-state access mode. The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length (in four-state access mode). The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 71
Specifications 2
1 4
3
5
MS_SCLKI
6
7
8
MS_SCLKO
11 9 10 11
MS_BS
12 12
MS_SDIO (output)
14
13
MS_SDIO (input) (RED bit = 0)
15 16
MS_SDIO (input) (RED bit = 1)
Figure 55. MSHC Signal Timing Diagram Table 32. MSHC Signal Timing Parameter Table
Ref No. 1 2 3 4 5 6 7 8 9 10 MS_SCLKI frequency MS_SCLKI high pulse width MS_SCLKI low pulse width MS_SCLKI rise time MS_SCLKI fall time MS_SCLKO frequency1 MS_SCLKO high pulse width1 MS_SCLKO low pulse width1 MS_SCLKO rise time1 MS_SCLKO fall time1 Parameter Minimum - 20 20 - - - 20 15 - - Maximum 25 - - 3 3 25 - - 5 5 Unit MHz ns ns ns ns MHz ns ns ns ns
MC9328MX1 Advance Information, Rev. 4 72 Freescale Semiconductor
Specifications
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No. 11 12 13 14 15 16 1. 2. MS_BS delay time1 MS_SDIO output delay time1,2 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4 Parameter Minimum - - 18 0 23 0 Maximum 3 3 - - - - Unit ns ns ns ns ns ns
3. 4.
Loading capacitor condition is less than or equal to 30pF. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin direction changes. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
3.17 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulsewidth modulator output (PWMO) external pin.
2a
System Clock
1 3b
2b 3a 4a
PWM Output
4b
Figure 56. PWM Output Timing Diagram Table 33. PWM Output Timing Parameter Table
Ref No. 1 2a 2b 1.8V +/- 0.10V Parameter Minimum System CLK frequency1 Clock high time1 Clock low time1 0 3.3 7.5 Maximum 87 - - Minimum 0 5/10 5/10 Maximum 100 - - MHz ns ns 3.0V +/- 0.30V Unit
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 73
Specifications
Table 33. PWM Output Timing Parameter Table (Continued)
Ref No. 3a 3b 4a 4b
1.
1.8V +/- 0.10V Parameter Minimum Clock fall time1 Clock rise time1 Output delay time1 Output setup time1
CL of PWMO = 30 pF
3.0V +/- 0.30V Unit Minimum - - 5 5 Maximum 5/10 5/10 - - ns ns ns ns
Maximum 5 6.67 - -
- - 5.7 5.7
3.18 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued to the SyncFlash is Load Command Register. A [7:0] determine which operation the command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the address to be programmed. The next command is Active which registers the row address and confirms the bank address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required. A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The bank and other address lines are driven to the selected address. The second command is Active which sets up the status register read. The bank and row addresses are driven during this command. The third command of the triplet is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
MC9328MX1 Advance Information, Rev. 4 74 Freescale Semiconductor
Specifications
1
SDCLK 2 3S CS 3
3S RAS 3S 3H CAS 3S 3H WE
3H
3H
4S ADDR
4H COL/BA 8 5 6 Data 7 3S
ROW/BA
DQ
DQM 3H
Note:
CKE is high during the read/write cycle.
Figure 57. SDRAM/SyncFlash Read Cycle Timing Diagram Table 34. SDRAM Timing Parameter Table
Ref No. 1 2 3 3S 1.8V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time 2.67 6 10.4 3.42 Maximum - - - - Minimum 4 4 10 3 Maximum - - - - ns ns ns ns 3.0V Unit
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 75
Specifications
Table 34. SDRAM Timing Parameter Table (Continued)
Ref No. 3H 4S 4H 5 5 5 6 7 7 7 8 1. 1.8V Parameter Minimum CS, RAS, CAS, WE, DQM hold time Address setup time Address hold time SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) 2.28 3.42 2.28 - - - 2.85 - - - tRCD1 Maximum - - - 6.84 6.84 22 - 6.84 6.84 22 - Minimum 2 3 2 - - - 2.5 - - - tRCD1 Maximum - - - 6 6 22 - 6 6 22 - ns ns ns ns ns ns ns ns ns ns ns 3.0V Unit
tRCD = SDRAM clock cycle time. The tRCD setting can be found in the MC9328MX1 reference manual.
MC9328MX1 Advance Information, Rev. 4 76 Freescale Semiconductor
Specifications
SDCLK 1 CS 3 2
RAS
6
CAS
WE 4 ADDR 5 7 COL/BA 8 DQ DATA 9
/ BA
ROW/BA
DQM
Figure 58. SDRAM/SyncFlash Write Cycle Timing Diagram Table 35. SDRAM Write Timing Parameter Table
Ref No. 1 2 3 4 5 6 7 1.8V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period1 Active to read/write command delay 2.67 6 10.4 3.42 2.28 tRP2 tRCD2 Maximum - - - - - - - Minimum 4 4 10 3 2 tRP2 tRCD2 Maximum - - - - - - - ns ns ns ns ns ns ns 3.3V Unit
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 77
Specifications
Table 35. SDRAM Write Timing Parameter Table (Continued)
Ref No. 8 9 1. 2. 1.8V Parameter Minimum Data setup time Data hold time 4.0 2.28 Maximum - - Minimum 2 2 Maximum - - ns ns 3.3V Unit
Precharge cycle timing is included in the write timing diagram. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual.
SDCLK 1 CS 3 2
RAS
6
CAS 7 7
WE 4 ADDR BA 5 ROW/BA
DQ
DQM
Figure 59. SDRAM Refresh Timing Diagram Table 36. SDRAM Refresh Timing Parameter Table
Ref No. 1 1.8V Parameter Minimum SDRAM clock high-level width 2.67 Maximum - Minimum 4 Maximum - ns 3.3V Unit
MC9328MX1 Advance Information, Rev. 4 78 Freescale Semiconductor
Specifications
Table 36. SDRAM Refresh Timing Parameter Table (Continued)
Ref No. 2 3 4 5 6 7 1. 1.8V Parameter Minimum SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 6 10.4 3.42 2.28 tRP1 tRC1 Maximum - - - - - - Minimum 4 10 3 2 tRP1 tRC1 Maximum - - - - - - ns ns ns ns ns ns 3.3V Unit
tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual.
SDCLK
CS
RAS
CAS
WE
ADDR
BA
DQ
DQM
CKE
Figure 60. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 79
Specifications
3.19 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer.
USBD_AFE (Output)
1
t ROE_VPO
t VMO_ROE 4
USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE
USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT
5
Figure 61. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
Ref No. 1 2 3 4 5 Parameter tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) tFEOPT; SE0 interval of EOP Minimum 83.14 81.55 83.54 248.90 160.00 Maximum 83.47 81.98 83.80 249.13 175.00 Unit ns ns ns ns ns
MC9328MX1 Advance Information, Rev. 4 80 Freescale Semiconductor
Specifications
Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) (Continued)
Ref No. 6 tPERIOD; Data transfer rate Parameter Minimum 11.97 Maximum 12.03 Unit Mb/s
USBD_AFE (Output)
USBD_ROE (Output)
USBD_VPO (Output)
USBD_VMO (Output)
USBD_SUSPND (Output)
USBD_RCV (Input) 1
tFEOPR
USBD_VP (Input) USBD_VM (Input)
Figure 62. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 38. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
Ref No. 1 Parameter tFEOPR; Receiver SE0 interval of EOP Minimum 82 Maximum - Unit ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 81
Specifications
3.20 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5 SCL 1 2
3
4
6
Figure 63. Definition of Bus Timing for I2C Table 39. I2C Bus Timing Parameter Table
Ref No. 1 2 3 4 5 6 1.8V +/- 0.10V Parameter Minimum Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum - 171 - - - - Minimum 160 0 10 120 320 160 Maximum - 150 - - - - ns ns ns ns ns ns 3.0V +/- 0.30V Unit
3.21 Synchronous Serial Interface
The MC9328MX1 processor contains two identical SSI modules. The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 65 through Figure 67 on page 84. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
MC9328MX1 Advance Information, Rev. 4 82 Freescale Semiconductor
Specifications 1
STCK Output
2
STFS (bl) Output
4
6
STFS (wl) Output
8 12
10
STXD Output
11
31
SRXD Input
32
Note:
SRXD input in synchronous mode only.
Figure 64. SSI Transmitter Internal Clock Timing Diagram
1
SRCK Output
3
SRFS (bl) Output
5
7
SRFS (wl) Output
9
13 14
SRXD Input
Figure 65. SSI Receiver Internal Clock Timing Diagram
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 83
Specifications 15 16
STCK Input
17
18
STFS (bl) Input
20
22
STFS (wl) Input
24
26
STXD Output
27
28
33
SRXD Input Note: SRXD Input in Synchronous mode only.
34
Figure 66. SSI Transmitter External Clock Timing Diagram
15 16
SRCK Input
17
19
SRFS (bl) Input
21
23
SRFS (wl) Input
25
29
SRXD Input
30
Figure 67. SSI Receiver External Clock Timing Diagram Table 40. SSI 1 Timing Parameter Table
Ref No. 1.8V +/- 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V +/- 0.30V Unit
Internal Clock Operation1 (Port C Primary Function)2 1 2 STCK/SRCK clock period1 STCK high to STFS (bl) high3 95 1.5 - 4.5 83.3 1.3 - 3.9 ns ns
MC9328MX1 Advance Information, Rev. 4 84 Freescale Semiconductor
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref No. 3 4 5 6 7 8 9 10 NOTES 1.8V +/- 0.10V Parameter Minimum SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low -1.2 2.5 0.1 1.48 -1.1 2.51 0.1 14.25 Maximum -1.7 4.3 -0.8 4.45 -1.5 4.33 -0.8 15.73 Minimum -1.1 2.2 0.1 1.3 -1.1 2.2 0.1 12.5 Maximum -1.5 3.8 -0.8 3.9 -1.5 3.8 -0.8 13.8 ns ns ns ns ns ns ns ns 3.0V +/- 0.30V Unit
11a 11b 12 13 14
0.91 0.57 12.88 21.1 0
3.08 3.19 13.57 - -
0.8 0.5 11.3 18.5 0
2.7 2.8 11.9 - -
ns ns ns ns ns
External Clock Operation (Port C Primary Function)2 15 16 17 18 19 20 21 22 23 24 25 26 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high 92.8 27.1 61.1 - - - - - - - - 18.01 - - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 81.4 40.7 40.7 0 0 0 0 0 0 0 0 15.8 - - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 ns ns ns ns ns ns ns ns ns ns ns ns
27a
8.98
18.13
7.0
15.9
ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 85
Specifications
Table 40. SSI 1 Timing Parameter Table (Continued)
Ref No. 27b 28 29 30 1.8V +/- 0.10V Parameter Minimum STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low 9.12 18.47 1.14 0 Maximum 18.24 28.5 - - Minimum 8.0 16.2 1.0 0 Maximum 16.0 25.0 - - ns ns ns ns 3.0V +/- 0.30V Unit
Synchronous Internal Clock Operation (Port C Primary Function)2 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 - - 13.5 0 - - ns ns
Synchronous External Clock Operation (Port C Primary Function)2 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns
2.
3.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (PC3 - PC8) and Port B alternate function (PB14 - PB19). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length.
Table 41. SSI 2 Timing Parameter Table
Ref No. 1.8V +/- 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V +/- 0.30V Unit
Internal Clock Operation1 (Port B Alternate Function)2 1 2 3 4 5 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 95 1.7 -0.1 3.08 1.25 - 4.8 1.0 5.24 2.28 83.3 1.5 -0.1 2.7 1.1 - 4.2 1.0 4.6 2.0 ns ns ns ns ns
MC9328MX1 Advance Information, Rev. 4 86 Freescale Semiconductor
Specifications
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref No. 6 7 8 9 10 1.8V +/- 0.10V Parameter Minimum STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 1.71 -0.1 3.08 1.25 14.93 Maximum 4.79 1.0 5.24 2.28 16.19 Minimum 1.5 -0.1 2.7 1.1 13.1 Maximum 4.2 1.0 4.6 2.0 14.2 ns ns ns ns ns 3.0V +/- 0.30V Unit
11a 11b 12 13 14
1.25 2.51 12.43 20 0
3.42 3.99 14.59 - -
1.1 2.2 10.9 17.5 0
3.0 3.5 12.8 - -
ns ns ns ns ns
External Clock Operation (Port B Alternate Function)2 15 16 17 18 19 20 21 22 23 24 25 26 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low 92.8 27.1 61.1 - - - - - - - - 18.9 - - - 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 81.4 40.7 40.7 0 0 0 0 0 0 0 0 16.6 - - - 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 ns ns ns ns ns ns ns ns ns ns ns ns
27a 27b
9.23 10.60
20.75 21.32
8.1 9.3
18.2 18.7
ns ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 87
Specifications
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref No. 28 29 30 1.8V +/- 0.10V Parameter Minimum STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low 17.90 1.14 0 Maximum 29.75 - - Minimum 15.7 1.0 0 Maximum 26.1 - - ns ns ns 3.0V +/- 0.30V Unit
Synchronous Internal Clock Operation (Port B Alternate Function)2 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 - - 16.5 0 - - ns ns
Synchronous External Clock Operation (Port B Alternate Function)2 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 - - 1.0 0 - - ns ns
2.
3.
All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 - PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input is selected from Port C alternate function. bl = bit length; wl = word length
3.22 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 x 32 image data receive FIFO, and a 16 x 32 statistic data FIFO.
3.22.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 69 on page 89 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 42 on page 89.
MC9328MX1 Advance Information, Rev. 4 88 Freescale Semiconductor
Specifications
1 VSYNC 7
HSYNC 2
5
6
PIXCLK
DATA[7:0]
Valid Data 3 4
Valid Data
Valid Data
Figure 68. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
1 VSYNC 7
HSYNC 2
5
6
PIXCLK
DATA[7:0]
Valid Data 3 4
Valid Data
Valid Data
Figure 69. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 42. Gated Clock Mode Timing Parameters
Ref No. 1 2 3 Parameter csi_vsync to csi_hsync csi_hsync to csi_pixclk csi_d setup time Minimum 9 * THCLK 3 1 Maximum - (Tp / 2) - 3 - Unit ns ns ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 89
Specifications
Table 42. Gated Clock Mode Timing Parameters (Continued)
Ref No. 4 5 6 7 Parameter csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk frequency Minimum 1 10.42 10.42 0 Maximum - - - 48 Unit ns ns ns MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: Rising-edge latch data max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
3.22.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data on the positive edge. Figure 71 on page 91 shows the timing diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative edge. The parameters for the timing diagrams are listed in Table 43 on page 91.
MC9328MX1 Advance Information, Rev. 4 90 Freescale Semiconductor
Specifications
1 VSYNC
6 4 5
PIXCLK
DATA[7:0]
Valid Data 2 3
Valid Data
Valid Data
Figure 70. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge
1 VSYNC
6 5 4
PIXCLK
DATA[7:0]
Valid Data 2 3
Valid Data
Valid Data
Figure 71. Sensor Output Data on Pixel Clock Rising Edge CSI Latches Data on Pixel Clock Falling Edge Table 43. Non-Gated Clock Mode Parameters
Ref No. 1 2 3 4 Parameter csi_vsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time Minimum 9 * THCLK 1 1 10.42 Maximum - - - - Unit ns ns ns ns
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 91
Specifications
Table 43. Non-Gated Clock Mode Parameters (Continued)
Ref No. 5 6 Parameter csi_pixclk low time csi_pixclk frequency Minimum 10.42 0 Maximum - 48 Unit ns MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and setup time, according to: max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore: max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns => max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns => max fall time allowed = 5 - 1 = 4ns Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time)
MC9328MX1 Advance Information, Rev. 4 92 Freescale Semiconductor
4 Pin-Out and Package Information
Table 44. MC9328MX1 BGA Pin Assignments
1 A B C 2 3 VSS 4 5 6 VSS SSI_RXCLK 7 8 9 10 NVDD3 BT11 11 BT5 BT7 BT3 BT1 BTRFVDD 12 13 QVDD4 VSS NC RVP RVM AVDD2 14 UIP UIN VSS 15 NC NC R1B 16
Freescale Semiconductor MC9328MX1 Advance Information, Rev. 4 93
VSS SD_DAT3 SD_CLK
USBD_AFE NVDD4 USBD_OE USBD_VP
UART1_RTS UART1_RXD SSI_TXCLK SPI1_SCLK UART1_TXD
A24 SD_DAT1 SD_CMD SIM_TX A23 D31 SD_DAT0 SIM_PD
USBD_RCV UART2_ CTS
UART2_RXD SSI_RXFS
BTRFGND BT8
D
A22 D30
D29
SIM_SVEN USBD_ SUSPND D26 A19 D23 D20 D19 D17 D15 A6 SD_DAT2 A16 D21 NVDD1 NVDD1 NVDD1 D14 SDCLK
USBD_VPO USBD_VMO SSI_RXDAT SPI1_SPI_RDY BT13
BT6
NC
NC
NC
R1A
R2B
E F G H J K L M
A20 A21 A18 D27 A15 A17 A13 D22 A12 A11 A10 D16 A8 A5 A7 D12
D28 D25 D24 A14 D18 A9 D13 D11
USBD_VM SIM_RST SIM_RX NVDD1 NVDD1 VSS NVDD1 VSS
UART2_RTS SSI_TXDAT UART2_TXD SSI_TXFS SIM_CLK VSS VSS VSS VSS RW
SPI1_SS SPI1_MISO
BT12 BT10 BT9 PS VSS NVDD2 TIN
BT4 BT2 CLS LD0 LD6 LD10 PWMO
NC REV
NC PY1
PY2 PX1 LP/HSYNC LD5 LD11 LD14 CSI_D1
PX2 LSCLK
R2A SPL_SPR
UART1_CTS SPI1_MOSI VSS NVDD1 NVDD1 CAS MA10 QVDD1 VSS NVDD2 TCK RAS
CONTRAST ACD/OE LD2 LD7 LD12 CSI_MCLK LD4 LD8 LD13 CSI_D0
FLM/VSYNC LD1 LD9 QVDD3 TMR2OUT CSI_D2 LD3 VSS LD15 CSI_D3 CSI_D5
RESET_IN BIG_ CSI_D4 ENDIAN RESET_ SF SDCKE1 DQM0 SDWE RESET_ BOOT2 OUT BOOT3 BOOT0
CSI_HSYNC CSI_VSYNC CSI_D6
N
A4
EB1
D10
D7
A0
D4
PA17
D1
DQM1
CSI_PIXCLK CSI_D7
TMS
TDI
P R T
A3
D9
EB0 A1 OE
CS3 CS4 CS5
D6 D8 CS2
ECB D5 CS1
D2 LBA CS0
D3 BCLK1 MA11
DQM3 D0 DQM2
TRST BOOT1 TRISTATE
I2C_SCL TDO EXTAL16M
I2C_SDA QVDD2 XTAL16M
XTAL32K EXTAL32K VSS
EB2 EB3 VSS A2
SDCKE0 POR CLKO AVDD1
1.
burst clock
Pin-Out and Package Information
Pin-Out and Package Information
4.1 MAPBGA Package Dimensions
Figure 72 illustrates the MAPBGA 14 mm x 14 mm x 1.30 mm package, which has 0.8 mm spacing between the pads. The device designator for the MAPBGA package is VH.
Figure 72. MC9328MX1 MAPBGA Mechanical Drawing
MC9328MX1 Advance Information, Rev. 4 94 Freescale Semiconductor
NOTES
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 95
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MC9328MX1/D Rev. 4 08/2004

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